| PART |
Description |
Maker |
| ASM5I9351G-32-LT ASM5I9351 ASM5I9351-32-ET ASM5I93 |
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
|
Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
http://
|
| CY29351AI CY29351AIT CY29351 |
2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
|
CYPRESS[Cypress Semiconductor]
|
| CY29949AXC CY29949AXCT CY29949AXI CY29949AXIT CY29 |
2.5V or 3.3V 200 MHz 1:15 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency Range: 0 MHz to 200 MHz; Outputs: 15; Operating Range: 0 to 70 C 29949 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
|
Cypress Semiconductor, Corp.
http://
|
| PDU54-1500 PDU54-2000 PDU54-1200M PDU54-1200MC4 PD |
Delay 1500 /-200 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 2000 /-400 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 1200 /-200 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 1000 /-200 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 200 /-60 ns, 4-BIT, ECL-interfaced programmable delay line
Delay 100 /-50 ns, 4-BIT, ECL-interfaced programmable delay line
|
Data Delay Devices Inc
|
| UPD424400LLA-A80 UPD42S4400LLA-A80 UPD42S4400LGS-A |
2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer
Clock Synthesizer with Differential SRC and CPU Outputs
Clock Generator for Intel® Grantsdale Chipset
x4 Fast Page Mode DRAM x4快速页面模式的DRAM
|
Vishay Intertechnology, Inc.
|
| CY23FP12-00211 CY3672-USB CY23FP12OXC-002 CY23FP12 |
200-MHz Field Programmable Zero Delay Buffer
|
Cypress Semiconductor
|
| CY2302SXI-1T |
Frequency Multiplier and Zero Delay Buffer; Voltage (V): 3.3/5.0 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 2; Operating Range: -40 to 85 C 23S SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
Frequency Multiplier and Zero Delay Buffer; Voltage (V): 3.3/5.0 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 2; Operating Range: -40 to 85 C
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| CY2SSTU87706 CY2SSTU877BVXC-43 CY2SSTU877BVXC-43T |
1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
SSTU SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
|
Cypress Semiconductor
CYPRESS SEMICONDUCTOR CORP
|
| DDU8F DDU8F-5175 DDU8F-5150 DDU8F-5020 DDU8F-5060 |
Total delay 6 /-1 ns, 5-TAP, TTL-interfaced fixed delay line
Total delay 16 /-2 ns, 5-TAP, TTL-interfaced fixed delay line
Total delay 12 /-2 ns, 5-TAP, TTL-interfaced fixed delay line
Total delay 8 /-2 ns, 5-TAP, TTL-interfaced fixed delay line
PASSIVE DELAY LINE, TRUE OUTPUT, DFP14
PASSIVE DELAY LINE, TRUE OUTPUT, DSO14
PASSIVE DELAY LINE, TRUE OUTPUT, DSO8
ACTIVE DELAY LINE, TRUE OUTPUT, DSO14
PASSIVE DELAY LINE, TRUE OUTPUT, DIP8 LOW PROFILE, DIP-8
ACTIVE DELAY LINE, TRUE OUTPUT, DFP14
5-TAP, TTL-INTERFACED FIXED DELAY LINE 5，技术咨询，与TTL接口固定延迟
From old datasheet system
Total delay 4 /-1 ns, 5-TAP, TTL-interfaced fixed delay line
|
DATA DELAY DEVICES INC
Data Delay Devices, Inc.
Electronic Theatre Controls, Inc.
|
| CY23S08SXC-1T |
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 140 MHz; Outputs: 8; Operating Range: 0 to 70 C 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
|
Cypress Semiconductor, Corp.
|
|
